In wired communications, optical communications, backplane routing, chip-to-chip interconnects, etc., many industry standards have been developed over the years, such as SATA, SONET, PCI Express, IEEE 1394b, USB3.0, HDMI, DVI, DisplayPort, etc. The technological backbone behind these industry standards is Serializer/Deserializer (“SerDes”) technology.
FIG. 1 shows a conventional Serializer/Deserializer (SerDes). The Serializer/Deserializer has a pair of functional blocks 10, 20 that convert data 30 from serial to parallel (at deserializer 20) and parallel to serial (at serializer 10). Serializer block 10 generally comprises an input latch 12 and a multiplexor (MUX) 14. The input latch 12 receives a multi-bit incoming data signal 11a-11n, and outputs data signals 13a-13n to the multiplexor 14. The multiplexor receives the data signals 13a-13n, and outputs a serial data stream 30 on differential bus 15 via buffer 16 to the deserializer block 20. Deserializer block 20 generally comprises a demultiplexor (DEMUX) 24 and an output latch 26. The demultiplexer (DEMUX) 24 receives the serial data stream 30 on differential bus 23 via buffer 22, and outputs data signals 25a-25n to the output latch 26. The output latch 26 outputs a multi-bit signal 27a-27n to a downstream processing unit. The benefits of conventional Serializer/Deserializer technology include relatively few wires, smaller board space, longer communication distances, and lower power consumption.
Generally, in most Serializer/Deserializer architectures, the data stream is sent from transmitter to receiver without an accompanying clock signal. The receiver (deserializer 20) first generates a clock signal from an approximate frequency reference. Subsequently, the receiver frequency-aligns and phase-aligns the clock signal to transitions embedded in the data stream 23. This process is commonly known as Clock Data Recovery (CDR), as shown in FIG. 2.
FIG. 2 shows a conventional SerDes architecture in which the receiver 130 includes a clock data recovery (CDR) circuit 140. The SerDes architecture of FIG. 2 comprises a transmitter 110, a board trace 120, and a receiver 130. The transmitter 110 outputs a serial data across the board trace 120 to the receiver 130. The receiver 130 generally comprises a package interface 135 and a clock and data recovery (CDR) circuit 140. The package interface 135 receives the data signal and transmits the data signal to the CDR circuit 140. The CDR circuit 140 outputs the data signal 145 and a recovered clock signal 146.
As illustrated in FIG. 2, the recovered clock 146 has to bear a frequency that matches the incoming data rate. Typically, difficulty occurs due to the incoming data being driven by a clock which is invisible to the CDR circuit 140. The task of the CDR circuit 140 is to find its frequency using the received data. The phase of the recovered clock generally has to be in the center of the data time window (e.g., see clock edges 150, 152, 154 and 156) for maximum safety margin. Furthermore, during the clock generation process, the timing jitter embedded in the incoming data has to be rejected as much as possible. Typically, several issues are addressed in CDR circuit 140, including frequency generation, clock-data alignment, and jitter tolerance.
FIG. 3 illustrates a generic transmitter (TX) 110 and receiver (RX) 130 pair that do not share a common frequency source. Typically, the CDR circuit adjusts the receiver 130 frequency to track the transmitter data rate (e.g., frequency). Generally, the transmitter 110 outputs a data signal 120 to the receiver 130. The receiver 130 receives the data signal 120. However, typically, there is a frequency offset between the transmitter 110 and the receiver 130. For example, the frequency 115 of the transmitter 110 may be f0+fos(t), and the frequency 132 of the receiver 130 may be f0. Furthermore, the frequency offset may not be stable, and may vary over time.
The transmitter-receiver pair of FIG. 3 illustrates a plesiochronous system, in which the significant instants (e.g., transitions) of the signals occur at nominally the same rate. Any variation of the signals' rate is constrained within a specified limit. For example, in a USB3 system, the transmitter 110 and the receiver 130 operate plesiosynchronously at the same nominal frequency, even though there may be a slight short-term frequency mismatch from time to time. This frequency mismatch leads to phase drifting.
Plesiochronous systems behave similarly to synchronous systems, except that the plesiochronous system must manage synchronization slips, which happen periodically due to the plesiochronous nature of the system. In general, the task of frequency matching between the transmitter 110 and the receiver 130 can be expressed mathematically, as shown in the following equation:Pt=Pr  (1)where Pt is the reciprocal of the frequency of the transmitter 110 and Pr is the reciprocal of the frequency of the receiver 130. The transmitter clock frequency is determined according to the following equation:ft(=1/Pt)  (2)
The receiver clock frequency is determined according to the following equation:fr(=1/Pr)  (3)
If the receiver CDR circuit worked perfectly, Equation (1) above will be satisfied in every data cycle. However, this is never the case, as a practical matter, because feedback is used in the CDR circuit. The compare-then-correct mechanism in feedback implies that it is mathematically impossible to recover the clock within the time frame of one data cycle. Thus, in actual systems, Equation (1) above can never be truly achieved between the transmitter 110 and the receiver 130 if investigated in every data cycle, and instead, Equation (1) is only approximately true in frequency matching cycle by cycle.
In CDR designs, since equation (1) cannot be satisfied on a cycle by cycle basis, the CDR circuit attempts to match frequencies over a relatively long term. Generally, a large (e.g., theoretically infinite) number of frequencies are produced by the CDR circuit in the receiver 130 side, and this large number of frequencies are used to track the transmitter frequency. In other words, the number of possible receiver frequencies “n” is large or infinite. In CDR circuit implementation, there are two approaches, analog CDR and digital CDR. In the analog CDR case, an analog voltage controlled oscillator (VCO) is used as the frequency generator in the CDR structure. This VCO can produce a theoretically infinite number of frequencies that can be used for tracking the transmitter frequency. In the digital CDR case, a digital controlled oscillator (DCO) is used as the frequency generator. A DCO can also produce a large number of frequencies. However, these frequencies are discrete.
FIG. 4 shows a traditional implementation of a clock data recovery (CDR) circuit 140 using a feedback mechanism. A transmitter (not shown) outputs a data signal 141 to a phase detector 142. The phase detector 142 detects the frequency and phase of the data signal 141 from the transmitter, and outputs a retimed data signal 143 and an offset signal to a charge pump 144. The charge pump 144 converts the offset signal into a current signal that can be fed to a loop filter 146. Subsequently, the loop filter 146 smoothes this signal, and outputs an adjustment signal to a voltage controlled oscillator (VCO) 148. The VCO 148 is a frequency generator in the receiver that receives the signal from the filter 146 and outputs a clock signal 149 with corresponding frequency. Furthermore, the VCO 148 outputs the same signal 149 to the phase detector 142 for the frequency and phase comparison between the transmitter data and receiver clock.
CDR circuits typically have a phase detector 142 providing a digital output, but the VCO 148 must receive an analog control signal (e.g., a voltage). Typically, in modern CDR implementations, the phase detector 142 is a binary type circuit rather than a linear type circuit due to the high speed operation of the phase detector 142. Therefore, a digital-to-analog conversion process is required in the forward path (i.e., from the phase detector 142 to the VCO 148). This process results in relatively greater demands for chip resources and power, and an increase in the amount of noise and/or electromagnetic interference (EMI).
Furthermore, the conventional CDR 140 has conflicting constraints in the design of the feedback loop. Filtering uncorrelated input jitter requires a relatively small loop bandwidth. However, suppression of the VCO noise requires a relatively large loop bandwidth.
This “Discussion of the Background” section is provided for background information only. The statements in this “Discussion of the Background” are not an admission that the subject matter disclosed in this “Discussion of the Background” section constitutes prior art to the present disclosure, and no part of this “Discussion of the Background” section may be used as an admission that any part of this application, including this “Discussion of the Background” section, constitutes prior art to the present disclosure.